Field of the Invention
The present invention relates to a multi-stage and feed forward compensated complimentary current field effect transistor amplifiers, enabling a charge-based approach that takes advantage of the exponential properties incurred in sub-threshold operation.
Description of Related Art
The new millennium brings with it a demand for connectivity that is expanding at an extremely rapid pace. By the end of year 2015, the number of global network connections will exceed two times the world population and it is estimated that in 2020 more than 30 billion devices will be wirelessly connected to the cloud forming the Internet of Things (or “IoT”). Enabling this new era are the revolutionary developments in mobile computing and wireless communication that have arisen over the last two decades. Following Moore's Law, development of highly-integrated and cost-effective silicon complementary metal oxide semiconductor (CMOS) devices allowed incorporation of digital and analog system elements, such as bulky Analog-to-Digital converters or transceivers, into a more cost effective single chip solution.
In the last few years, however, while digital circuits have largely followed the predicted path and benefited from the scaling of CMOS technology into ultra-deep submicron (sub-μm), analog circuits have not been enabled to follow the same trend, and may never be enabled without a paradigm shift in analog design. Analog and radio frequency (or “RF”) designers still struggle to discover how to make high-performance integrated circuits (or “ICs”) for ultra-deep sub-μm feature sizes without losing the benefits of shrinking size; including reduced power, compact footprint, and higher operational frequencies. Truly a paradigm shift is needed to break through the established science of analog design to meet the system on chip (SoC) demands of the new millennium.
Prior Art
The core building block of analog circuits is the amplifier. Discrete component amplifiers are free to use resistors, capacitors, inductors, transformers, and non-linear elements as well as various types of transistors. Unwanted parasitics between various components are normally negligible. However, in order to build amplifiers within an integrated circuit, the normal analog circuit components are not readily available, and often take special IC process extensions to obtain these circuit elements if at all. The parasitics on integrated circuit amplifiers are severe due to their close proximity and being coupled together through the silicon wafer they are integrated into. Moore's law IC process advancements are focused on digital, microprocessor, and memory process development. It takes a generation (˜18 months) or two to extend the IC process to incorporate analog components, thus analog functionality is generally not included on the latest process single chip systems. These “mixed-mode” IC processes are less available, vender dependent, and more expensive as well as being highly subject to parametric variation. It takes substantial engineering to include sparse analog functionality on any IC which becomes specific to its IC vender and process node. Because analog circuitry is carefully and specifically designed or arranged for each process node, such analog circuitry is highly non-portable. Reprobating this limitation, analog circuit design engineers are becoming scarce and are slowly retiring without adequate replacements.
Operational Amplifiers (or OpAmps) are the fundamental IC analog gain block necessary to process analog information. OpAmps make use of a very highly matched pair of transistors to form a differential pair of transistors at the voltage inputs. Matching is a parameter that is readily available on an integrated circuit, but to approach the required level of matching, many considerations are used: like centroid layout, multiple large devices, well isolation, and physical layout techniques among many other considerations. Large area matched sets of transistors are also used for current mirrors and load devices. OpAmps require current sources for biasing. OpAmps further require resistor and capacitor (or RC) compensation poles to prevent oscillation. Resistors are essential for the “R” and the value of the RC time constant is relatively precise. Too big value for a resistor would make the amplifier too slow and too small results in oscillation. Constant “bias” currents add to the power consumed. In general, these bias currents want to be larger than the peak currents required during full signal operation.
As IC processes are shrunk, the threshold voltages remain somewhat constant. This is because the metal-oxide-semiconductor (or MOS) threshold cutoff curve does not substantially change with shrinking of the IC processes and the total chip OFF leakage current must be kept small enough to not impact the full-chip power supply leakage. The threshold and saturation voltage tends to take up the entire power supply voltage, not leaving sufficient room for analog voltage swings. To accommodate this lack of signal swing voltage, OpAmps were given multiple sets of current mirrors, further complicating their design, while consuming more power and using additional physical layout area. This patent introduces amplifier designs that operate even better as power supply voltages are shrunk far below 1 volt.
The conventional MOS amplifier gain formation is an input voltage driving a trans-conductance (gm) which converts the input voltage into an output current. This output current then drives an output load which is normally the output of a current source for the purpose of establishing a high load resistance. This high resistance load converts the output current back into an output voltage. The equivalent output load resistance is actually the parallel combination of the load current source transistor and the amplifier output transistors. In order to keep this equivalent load resistance high to provide the required voltage gain, these load transistors must be very long, but to drive enough current these transistors must be very wide also, thus very large transistors are necessary. It also might be noted that the load resistance the amplifier output drives is additional parallel resistance that reduces the voltage gain. It should also be noted that a load capacitance interacts with the amplifiers output resistance, modifying the AC performance. What is actually needed is exactly the inverse operating principle, which the present invention is about. FIG. 1a is a transistor level schematic diagram of a high-quality MOS IC OpAmp as a baseline reference (from the Wiley textbook: Analysis and Design of Analog Integrated Circuits by Gray and others, 4th edition pg. 482) which is used for comparison in the description of the amplifiers illustrated herein.
The baseline comparisons are (all made in an 180 nm IC process) in the form of performance plots as in: a Bode Gain-Phase plot over frequency FIG. 1b, when Vdd=1.8 Volts and Rcmp=700 ohms. Wherever possible all the axis scales for each of these three comparison plots are kept the same. A readily available 180 nm process was selected for comparison of all the comparative examples in this document because the conventional prior art amplifiers work best and have had the most usage and have mature mixed-mode IC process extensions offered which are required for conventional analog. Also as the IC process is shrunk and the power supply voltage is decreased, this is where the implementations of the present invention become highly beneficial.
Normally MOS amplifiers operate within a square-law relationship due to the strong inversion MOS transistor square-law characteristics; these are not very well defined or predictably stable to the degree that analog circuits need. Exponential-law operation, like bipolar transistors operation is higher gain, stable, and well defined. At very weak operating conditions, MOS transistors convert to exponential operation, but they are too slow to be of very much use. Furthermore, the “moderate-inversion” transition between these two operating mode provide non-linarites that lower the quality of analog MOS circuits. At the threshold voltage, where MOS transistors operate around, is where 50% of the current is square-law and the other 50% is exponential. This is the definition of threshold voltage in the latest MOS simulation equations. Full exponential MOS operation at high speed would provide higher gain that is predictable, stable, and well defined. This patent is about amplifiers that operate in the exponential mode.
To understand the prior art, let's begin with a discussion of Weak vs. Strong inversion. Referring to FIGS. 1e and 1f, weak inversion is the range where most designers would consider the transistor to be OFF:                Drain to Source voltage is small (on the order of 100 mV);        The gate G (or 17s) is at a similar small potential (typically less than 300 mV);        This creates a surface conduction layer, of uniform depth from source S to drain D;        The conductivity of this surface layer is exponential with respect to the Gate G voltage;        This allows operation over many decades (about 6) of dynamic range;        The channel appears as a moderate value resistor (100+s of K-Ohms); and        The uniform depth conduction channel promotes an exponentially higher gain but with a speed penalty (due to low charge density in the conduction channel).        
Strong inversion (referring to FIGS. 1g & 1h) is characterized by a graduated conduction channel, deeper near the Source and shallow near at the Drain:                Drain to Source voltage is larger than the Gate to Source voltage Vg of FIG. 1g and threshold Vthreshold in FIG. 1h (typically in excess of 400 mV);        The Gate 17u is operated above its threshold voltage Vthreshold;        This creates a conduction channel that is deeper at the Source and tapers to near pinch-off at the Drain 12u;        The resulting conduction layer behaves with a Square-law response to the gate voltage at the Gate 17u;        Dynamic range is limited to about 3 decades as compared to weak inversion;        The channel 12g appears as an adjustable current source (high value resistor); and        The wedge shape of the conduction channel 12g provides higher speed than weak inversion because of higher charge density in the conduction channel.        
Now, referring back to FIG. 1e, which shows the channel 12e development under weak inversion conditions. The conduction channel 12e has a relatively even distribution of carriers over its entire length and width. Note that the conduction depth 10s of the entire channel is the same as the pinch-off area 12u on the right side of FIG. 1g. This thin conduction layer contributes a significant amount of noise because the channel current travels along the surface where charge carrier defect traps are concentrated. The Gate 17s to channel voltage Vg in FIG. 1e has a strong (exponential) effect on the density of carriers in this conduction layer.
FIG. 1g shows the channel 12u development under Strong inversion conditions. The higher potential difference between Source and Drain over the gate 17u causes “channel length modulation” (the flat part of the channel 12u), resulting in pinch-off near the drain diffusion where the channel reaches a thin layer near 12u. The pinch-off region 12u (where the carriers are forced to the top of the channel) imparts significant noise by means of surface defect carrier traps. The higher the drain voltage Vd, the longer the pinch-off region and thus the higher the contributed noise, thus it is desired to keep this voltage low for low noise contribution to the channel current. Other effects such as velocity saturation and hot electron jumping over into the gate oxide are noted around this thin saturated pinch-off region, thus it would be highly desirable to minimize this region by lower voltage and semiconductor doping profiles.
FIG. 1h shows a characteristic plot which approaches a “constant current” relationship between drain current Id and drain voltage Vds with a fixed Gate voltage Vg on the gate G. It is to be noted that the drain voltage Vds spans a large range of nearly the power supply voltage Vdd, while maintaining the same current as opposed to the limited drain voltage range of FIG. 1f. 
FIG. 1i to 1k illustrate a prior art MOS structure, commonly known as a CMOS inverter, that turns out to actually combine both modes of operation. A pair of MOSFETs with opposite conductivities, PFET and NFET, are complementary connected with each other. For example, the input 10i, 10j, 10k is connected to both the gate control terminal of PFET and the gate control terminal of NFET, the source of PFET is connected to power supply (+), while the source terminal of NFET is connected to power supply (−); and the drain of PFET and the drain of NFET connected together for Vout 19i. 
FIG. 1j shows the structure related to a physical layout abstraction shown in FIG. 1k, which is 2×strength CMOS or two-finger inverter of prior art. As stated above, gate terminals of PFET and NFET are connected together to receive Vinput 10j and 10k and the drain terminals of PFET and NFET are connected together for producing Voutput 19j and 19k. The layout shown in FIG. 1k structurally corresponds to that of FIG. 1i. As it can be seen, to minimize various shortcoming from the conventional FET layouts, such as minimizing parasitic output capacitance, the source terminal of PFET, for example, is split into two source terminals S+ and S+, and the drain terminal D+ 12k is displaced therebetween for forming a pair of parallel channels 14k and 16k between S+ and D+ 12k; p-channel region of the gate G covers the parallel channels 14k and 16k. Divided by the well border WB, NFET is also provided with a pair of source terminals, S− and S−, and the drain terminal thereof, D− 11k is displaced therebetween for forming a pair of parallel channels 13k and 15k between S− and D−; n-channel region of the gate G further covers the parallel channels 13k and 15k. Drains 12k and 11k are connected therebetween through metal work 18k and forms Voutput 19k. 
A 3-dimensional prospective view of this MOS transistor structure is shown in FIG. 1m, while cross sectional view at section AA in FIG. 1m is shown in FIG. 1n. This structure is inherent in a 2× or two-finger inverter as shown in FIGS. 1j and 1k. As it can be seen therein at the parallel channels 14k and 16k in PFET and the parallel channels 13k and 15k, all of these channels taper from the drains D+, D− to the sources S+, S−.
Although similar MOS structures appear in prior art, no significant exploitation of many of its unique properties are known or published. In addition, proper biasing remains as a problem(s) for its operation(s). A deeper understanding of the internal mechanisms resulted in discovery of many desirable applications (enabling superior operation at deep-sub-micron scale), including an approach to proper biasing that takes advantage of natural equilibrium. This natural equilibrium is the result of a “Band-Gap” voltage reference mechanism, again functional at deep-sub-micron scale.
Referring to FIGS. 1p and 1q, some references show a MOS field effect transistor device with two identical regions 13p/13q and 15p/15q of like “conductivity type” separated by a diffusion region 11p (designated as Z for Low Impedance in the prior art). Multiple papers by Bedabrata Pain/R Schober, Jet Propulsion Lab and Jacob Baker/Vishal Saxena, Boise State University, including Pain, Bedabrata et al., “A Self-Cascoding CMOS Circuit for Low-Power Applications”, Center for Space Microelectronics Technology Jet Propulsion Laboratory, California Institute of Technology, contain such references, but these references do not exploit any opportunities as shown in this document, especially when complementary devices like this are combined into a single composite device as will be explained in this invention. Such configurations have been called self-cascading or split-length devices. The two regions of such a configuration are arranged between source and a drain diffusions and have both a high impedance common gate connection and a low impedance connection to the mid channel regions. This low impedance mid channel control input, when exploited as outlined in this document, enables an entirely new set of analog design methods.
Although a cascade amplifier can be found in prior art, the prior art does not contain a complementary pair of cascade transistors connected as a totem-pole. With this simple compound structure, feedback from the output to the input can be used to self-bias the resulting inverter into its linear mode. As mentioned above, biasing of an amplifier has always been problematic; however, the novel and inventive self-biasing structure of the present invention addresses such an issue. Advantages of the configuration of the present invention (referred to as a complementary iFET or CiFET) are many, including, but not limited to:                Gain of the single stage is maximum when the output is at the midpoint (self-bias point);        The gain of a single CiFET stage is high (approaching 100), therefore, while the final output may swing close to the rails, its input remains near the midpoint. The stage before that, because of the high gain, operates its input and output near the mid-point (“sweet-spot”) where the gain is maximized. So too for each of the preceding stages;        Slew rate and symmetry are maximized where the channel current is highest (near the mid-point);        Noise is minimized where the channel current is highest (near the mid-point); and        Parasitic effects are negligible where the voltage swing is small.        
When the gate input signal moves in one direction, the output moves in the inverse direction. For example; a positive input yields a negative output, not so much because the N-channel device is turned on harder, but rather because the P-channel device is being turned off. Thevenin/Norton analysis shows that the current through the P and N devices must be exactly the same, because there is nowhere else for drain current in one transistor to go except through the drain of the complementary transistor; however the voltage drop across those devices does not have to be equal, but must sum to the power supply voltage. Due to the super-saturated source channel, these voltages are tied together exponentially. This is even more evident at low power supply voltages where the voltage gain peaks. This means that the gate-to-source voltage is precisely defined by the same and only drain current going through both transistors. Exponentials have the unique physical property like a time constant, or “half-life;” It does not matter where we are at a given point of time, a time constant later we will be a fixed percentage closer to the final value. This is a “minds-eye” illustration of the primary contributor to output movement in response to input change. This same current balance of gate-to-source operating voltages also indicates why the “sweet-spot” in the self-biased amplifier is so repeatable. In effect it is used as a differential pair-like reference point to the amplifier input signal.
It is to be noted that during the transition from vacuum tubes to bipolar transistors the industry underwent a major paradigm shift, learning to think in terms of current rather than voltage. With the advent of FETs & MOSFETs the pendulum swing is back toward thinking in terms of voltage, but much knowledge has been lost or forgotten. Herein is contained the rediscovery of some old ideas as well as some new ones, all applied to the up-coming “current” state of the art. It is believed that the inherent simplicity of the present invention speaks to their applicability and completeness.
A first issue may be that there is always a need for a little analog functionality, yet nearly all analog performance metrics of a MOS transistor are remarkably poor as compared to that of a Bipolar transistor. The industry has made MOS devices serve by employing extensive “work-arounds.” Conventional analog design is constrained by one or more of the followings:                Power supply voltages sufficient to bias the stacked thresholds, and transistors large enough to supply the necessary output drive current while still providing the high output impedance required for linearity and gain (gm*RL).        Lack of analog IC process extensions (unavailable at nanometer scale) are required for linear signals, let alone with the enhanced performance demonstrated herein.        Resistors, inductors, and large capacitors are mostly non-existent for analog designs in newer IC processes.        
In contrast, bipolar transistors can be made to have high gain (β), wider bandwidth, wider dynamic range (many decades, from near the rails down to the noise floor), better matching (found in differential pairs), and band-gap references. Junction FETs, which operate with sub-surface channel conduction below the surface defects, have lower noise than bipolar transistors. Likewise the CiFET super-saturated source channel operates primarily below the defects at the channel surface underneath the gate oxide.
MOS designs are poorer in the above areas but have their own extreme advantages, including, but not limited to:                MOS devices are small and relatively simple        highly scalable        high speed        low power        ultra-dense/high functionality systems on a chip, where Bipolar designs cannot go (deep sub-μm scale).        
Accordingly, building analog circuits on an IC has always been problematic. Engineering around poorly performing analog components has been the overriding objective for analog IC designers since analog circuits have been integrated. This drove the need for digital signal processing with algorithm development yielding digital magic.
Today the real-world of analog circuit design, signals still need to be converted on both the front and back end of signal processing systems. This need has become a road-block at deep sub-μm scale.
Another problem may be that solid-state amplifiers have been notoriously non-linear since their inception. To make them linear, increased open loop gain (with levels significantly higher than is ultimately needed) is traded for control over actual circuit gain and linearity through the use of a closed loop (feedback). A closed loop amplifier requires negative feedback. Most amplifier stages are inverting, providing the necessary negative feedback. A single stage inverter, with a closed loop, is stable (does not oscillate). Increased loop gain requires stages be added such that there are always an odd number of stages (sign is negative), to provide the necessary negative feedback. While a single stage amplifier is inherently stable, three stages and most definitely five stages are unstable (they always oscillate—because they are ring oscillators).
The problem then is how to properly compensate a multi-stage closed loop amplifier while maintaining a reasonable gain-bandwidth product. This is particularly difficult at deep-sub-micron scale where circuit stages must be simple in their design. The severely limited power supply voltages preclude the use of conventional analog design approaches. Additionally, it is desirable to avoid reliance upon analog extensions but rather to accomplish the necessary analog functions using all digital parts, to improve yields and decrease costs. Using all digital parts allows analog functions at process nodes that do not yet have analog extensions, and may never have them.
There is a long felt need for low-cost/high-performance systems integrated on a single chip for affordable high-volume devices such as the Internet of things, smart-sensors, and other ubiquitous devices.